Add clock board i2c interface #443
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Previously you could not know from which address the wishbone bus was reading and could not stall acknowledgements.
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This test should mirror FincFdecTests.hs but in software. Since HITL tests use a VIO, the current test is communicated to the CPU using a control register. The CPU communicates the status of the test back to the hardware using a status register, so it can be captured by the VIO. The frequency adjustments are slower over I2C compare to the dedicated pins on the external clock board (Si5395J-A-EVB). To speed up the test, the step size changed from 1ppb to 1ppm.
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This PR aims to program the clock chip on the FMC board.
We currently use the Skyworks Si5395J-A-EVB board as our external clock with frequecy adjustment. We also have a Trenz Electronic TEF0008 FMC, which we use for its 4 SFP ports. This board has a similar low jitter programmable clock generator (Si5345-D), but using this clock generator requires some changes.
The two major differences are programming the clock generator and the Finc and FDec signals. On the Skyworks board, we used SPI to program the clock generator, although it also could have been programmed using I2C. For the Finc and Fdec signals the dedicated pins were used, which worked using a pulse per Finc/Fdec.
On the Trenz FMC, we need to use I2C to program the clock generator. This board does not have dedicated pins for Finc/Fdec, and thus those signals also need to be send over I2C.
Issue #411
TODO
The current implementation does not work, as I2C transactions are not acknowledged (rust code reports
I2CError::NotAcknowledged). Since the I2C core in clash-cores passes tests, there is probably a bug in the I2C Wishbone interface (i2cWb). Debugging this problem is probably faster when the use GDB to program the Risc core (and for breakpoints).i2cWb)probe_test_doneis not deasserted after first HITL test